1. Field of the Invention
The present invention is related to chip designs of integrated circuits, more particularly to designs of graphic engine chips for drawing processing.
2. Description of Related Art
Graphic engine chips are used in ICs (integrate circuits) to help a processor, such as CPU, to expedite processing of drawing. A conventional graphic engine architecture in an IC is shown in FIG. 1. The graphic engine chip includes a GE CMD FIFO (Graphic Engine Command First-in First-out buffer) 100, a GE (Graphic Engine) 101, a display memory 102, a display controller 103, a GE memory 105, and a DMA (Direct Memory Access) controller 106. The GE CMD FIFO 100, the GE 101, the display memory 102, and the display controller 103 are coupled one after another. After coupling the GE memory 105 with the DMA controller 106, the one terminal of the GE memory 105 is coupled to the GE 101 and the other terminal of the DMA controller 106 is connected to the display memory 102.
In order to further understand the conventional Graphic Engine chip, a working process of the graphic engine chip is provided in FIG. 2. At 200, the processor is configured or caused to send drawing instructions to the GE CMD FIFO 100. The GE CMD FIFO 100 receives and buffers the drawing instructions therein at 201. When the GE 101 is free, it fetches at 202 the drawing instructions buffered in the GE CMD FIFO 100 in accordance with a sequence of the instructions received in the GE CMD FIFO 100.
At 203, the GE 101 executes the fetched instructions to edit drawing data in the display memory 102. Lots of calculations are needed when the GE 101 executes these drawing instructions. Hence, it requires the GE memory 105 to preserve the drawing data in the GE 101 temporarily. The display memory 102 at 204 preserves the edited drawing data and exports them to the displayer 104 by means of controlling of the display controller 103. At 205, a displayer 104 displays pictures in accordance with the received drawing data.
The DMA controller 106 may be used to control transmission of the drawing data when a large set of the drawing data needs to be transmitted between the display memory 102 and the GE 101. In this way, the drawing data can be transmitted from the GE memory 105 to the display memory 102 via the DMA controller 106, thereby saving the source of the GE 101.
It can be noted in the conventional graphic engine architecture and its applications that the drawing instructions sent by the processor do not contain time information. The GE CMD FIFO 100 buffers the drawing instructions one after another sequentially. Accordingly, the GE 101 executes the drawing instructions sequentially in the GE CMD FIFO 100. A whole drawing process, however, requires many executions of the instructions in the graphic engine chip operating according to predefined time intervals. However, a time interval between every two drawing instruction executions can not be controlled by the graphic engine chip. Thus, the processor has to send instructions per time intervals so that the executing time of the drawing instructions can be controlled.
For this reason, in order for the GE to execute every drawing instruction properly in time and at the same time not to be interrupted, it is often required that the processor controls the execution time of each drawing instruction and sends the drawing instructions on time. This increases the interruption and reduces the working efficiency of the processor.
In summary, the conventional graphic engine chip and its applications have at least some of the following disadvantages. Firstly, the underlying architecture can cause a processor connected to the graphic engine chip, CPU for instance, to respond to the graphic engine chip too frequently and thus increases the loading of the processor. Secondly, the time accuracy of the drawing process by the graphic engine chips depends on the response of the processor, thus difficult to control the whole drawing process accurately.
Thus there is a need for an efficient graphic engine architecture that impacts less on a processor coupled thereto.